522 search results - page 33 / 105 » A Note on Designing Logical Circuits Using SAT |
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitor...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Reversible quantum logic plays an important role in quantum computing. In this paper, we propose an approach to optimally synthesize quantum circuits by symbolic reachability anal...
DFT
2000
IEEE
13 years 11 months ago
2000
IEEE
Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design highperformance processors. However: dom...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementation...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Nanowire crossbar is one of the most promising circuit solutions for nanoelectronics. We show nanowire crossbars do not scale well in terms of logic density and speed. We conseque...