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» A Note on Designing Logical Circuits Using SAT
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ROBIO
2006
IEEE
469views Robotics» more  ROBIO 2006»
14 years 2 months ago
FPGA-Implementation of Inverse Kinematics and Servo Controller for Robot Manipulator
- The implementation of inverse kinematics and servo controller for robot manipulator using FPGA (Field Programmer Gate Array) is investigated in this paper. Firstly, the mathemati...
Ying-Shieh Kung, Kuan-Hsuan Tseng, Chia-Sheng Chen...
ICCAD
1996
IEEE
140views Hardware» more  ICCAD 1996»
14 years 4 days ago
Register-transfer level estimation techniques for switching activity and power consumption
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...
Anand Raghunathan, Sujit Dey, Niraj K. Jha
DFT
2004
IEEE
93views VLSI» more  DFT 2004»
13 years 11 months ago
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
14 years 4 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
DAC
2002
ACM
14 years 9 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...