278 search results - page 3 / 56 » A Novel Approach to Improve the Performance of Interconnecti... |
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— The main thesis of this paper is to perform a reliability based performance analysis for a shared latch inserted global interconnect under uncertainty. We first put forward a ...
ICC
2008
IEEE
14 years 1 months ago
2008
IEEE
—Layered streaming in overlay networks has drawn great interests since not only can it accomodate large scales of clients but also it handles client heterogeneities. However, to ...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
TVLSI
2010
13 years 2 months ago
2010
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...