Sciweavers

27 search results - page 2 / 6
» A Quality-Driven Design Approach for NoCs
Sort
View
CODES
2007
IEEE
15 years 6 months ago
Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels
In this paper, we propose an efficient technique for run-time application mapping onto Network-on-Chip (NoC) platforms with multiple voltage levels. Our technique consists of a re...
Chen-Ling Chou, Radu Marculescu
DSD
2009
IEEE
152views Hardware» more  DSD 2009»
15 years 8 months ago
ARROW - A Generic Hardware Fault Injection Tool for NoCs
Todays NoCs are reaching a level where it is getting very hard to ensure 100% of functionality. Consequently, fault tolerance has become an important aspect in todays design techn...
Michael Birner, Thomas Handl
DAC
2010
ACM
15 years 7 months ago
Trace-driven optimization of networks-on-chip configurations
Networks-on-chip (NoCs) are becoming increasingly important in general-purpose and application-specific multi-core designs. Although uniform router configurations are appropriate ...
Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Su...
ASPDAC
2009
ACM
108views Hardware» more  ASPDAC 2009»
15 years 11 months ago
Synthesis of networks on chips for 3D systems on chips
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...
Srinivasan Murali, Ciprian Seiculescu, Luca Benini...
NOCS
2010
IEEE
15 years 2 months ago
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
Samuel Rodrigo, Jose Flich, Antoni Roca, Simone Me...