209 search results - page 17 / 42 » A Systematic Approach for Designing Testable VLSI Circuits |
150
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GLVLSI
2010
IEEE
15 years 8 months ago
2010
IEEE
Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising directio...
112
Voted
ICCD
2005
IEEE
16 years 5 days ago
2005
IEEE
Abstract— Noise induced by impedance discontinuities from VLSI packaging is one of the leading challenges facing system level designers in the next decade. The performance of IC ...
107
Voted
ICCD
2007
IEEE
16 years 5 days ago
2007
IEEE
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globa...
129
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GLVLSI
2008
IEEE
15 years 9 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
126
Voted
DAC
2003
ACM
16 years 4 months ago
2003
ACM
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) th...