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» A Systematic Approach for Designing Testable VLSI Circuits
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GLVLSI
2006
IEEE
193views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
ARITH
2009
IEEE
14 years 2 months ago
Unified Approach to the Design of Modulo-(2n +/- 1) Adders Based on Signed-LSB Representation of Residues
Moduli of the form 2n ± 1, which greatly simplify certain arithmetic operations in residue number systems (RNS), have been of longstanding interest. A steady stream of designs fo...
Ghassem Jaberipur, Behrooz Parhami
GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
14 years 25 days ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi
DAC
2006
ACM
14 years 8 months ago
Standard cell characterization considering lithography induced variations
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
Ke Cao, Sorin Dobre, Jiang Hu
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 25 days ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee