209 search results - page 39 / 42 » A Systematic Approach for Designing Testable VLSI Circuits |
ISLPED
2009
ACM
14 years 2 months ago
2009
ACM
Many techniques for power management employed in advanced RTL synthesis tools rely explicitly or implicitly on observability don’t-care (ODC) conditions. In this paper we presen...
ISCAS
1999
IEEE
13 years 12 months ago
1999
IEEE
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
VLSID
2004
IEEE
14 years 8 months ago
2004
IEEE
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
ISPD
2003
ACM
14 years 29 days ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
We propose Satisfiability Checking (SAT) techniques that lead to a consistent performance improvement of up to 3x over state-ofthe-art SAT solvers like Chaff on important problem ...