228 search results - page 21 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
ISLPED
1996
ACM
14 years 23 days ago
1996
ACM
This paper proposes a 0.5V / 100MHz / sub-5mW-operated 1-Mbit SRAM cell architecture which uses an overVCC grounded data storage (OVGS) scheme. The key target of OVGS is to minimi...
ERSA
2006
13 years 10 months ago
2006
Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much l...
VLSID
2006
IEEE
14 years 9 months ago
2006
IEEE
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
DAC
2001
ACM
14 years 9 months ago
2001
ACM
In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access and data transfer. Thus, buses should be d...
DAC
2004
ACM
14 years 10 days ago
2004
ACM
This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests ...