228 search results - page 28 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
CASES
2007
ACM
2007
ACM
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
14 years 19 days ago
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
DAC
2004
ACM
14 years 9 months ago
2004
ACM
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
VLSISP
2010
13 years 7 months ago
2010
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementatio...
ISCA
2010
IEEE
14 years 1 months ago
2010
IEEE
Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to bes...