228 search results - page 31 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
ISSS
1995
IEEE
14 years 5 days ago
1995
IEEE
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been dev...
ISQED
2006
IEEE
14 years 2 months ago
2006
IEEE
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
In this paper, a Triangularization Based Structure preserving (TBS) model order reduction is proposed to verify power integrity of on-chip structured power grid. The power grid is...
HPCC
2007
Springer
14 years 2 months ago
2007
Springer
Abstract. Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. The embedded processors need to efï¬...
EH
2002
IEEE
14 years 1 months ago
2002
IEEE
The availability of SiGe HBT devices has opened the door for Gigahertz FPGAs. Speeds over 5GHz have been reported. However, to make the idea practical, serious power management an...