228 search results - page 3 / 46 » A bipartition-codec architecture to reduce power in pipeline... |
GLVLSI
2003
IEEE
14 years 22 days ago
2003
IEEE
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and c...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation....
VLSID
2006
IEEE
14 years 7 months ago
2006
IEEE
A low power multilevel interconnect architecture that uses wave-pipelined multiplexed (WPM) interconnect routing is proposed in this paper. WPM takes advantage of existing interco...
ISLPED
2004
ACM
14 years 26 days ago
2004
ACM
The quadratic relationship between voltage and energy has made dynamic voltage scaling (DVS) one of the most powerful techniques to reduce system power demands. Recently, techniqu...
DAC
1996
ACM
13 years 11 months ago
1996
ACM
In this paper, we describe a technique for power reduction in sequential circuits. Existing signals in the circuit are used to selectively disable some of the registers so that a ...