802 search results - page 2 / 161 » A comparative study of power efficient SRAM designs |
VLSI
2005
Springer
14 years 11 days ago
2005
Springer
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption a...
VLSID
2010
IEEE
13 years 10 months ago
2010
IEEE
A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nanoCMOS static random access memory (SRAM) is presented. A 45nm single-end...
SOCC
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper, new SRAM cell design methods for FinFET technology are proposed. One of the most important features of FinFET is that the independent front and back gate can be bia...
VLSISP
2008
13 years 6 months ago
2008
This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particula...
GLVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...