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» A comparative study of power efficient SRAM designs
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VLSID
2009
IEEE
119views VLSI» more  VLSID 2009»
16 years 6 months ago
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems
Abstract-- Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a ...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...
ISCAS
2007
IEEE
94views Hardware» more  ISCAS 2007»
16 years 4 days ago
Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM
Abstract— We study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above wh...
Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M....
MTDT
2006
IEEE
154views Hardware» more  MTDT 2006»
15 years 12 months ago
SRAM Cell Current in Low Leakage Design
This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby p...
Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, C...
SOCC
2008
IEEE
169views Education» more  SOCC 2008»
16 years 7 days ago
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies
— Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra...
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Sar...
DAC
2009
ACM
16 years 6 months ago
Fault models for embedded-DRAM macros
In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first star...
Ching-Yu Chin, Hao-Yu Yang, Mango Chia-Tso Chao, R...