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» A controller testability analysis and enhancement technique
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DATE
1997
IEEE
124views Hardware» more  DATE 1997»
14 years 3 months ago
A controller testability analysis and enhancement technique
This paper presents a testability analysis and improvement technique for the controller of an RT level design. It detects hard-to-reachstates by analyzing both the data path and t...
Xinli Gu, Erik Larsson, Krzysztof Kuchcinski, Zebo...
TCAD
1998
119views more  TCAD 1998»
13 years 10 months ago
A controller redesign technique to enhance testability of controller-data path circuits
—We study the effect of the controller on the testability of sequential circuits composed of controllers and data paths. We show that even when all the loops of the circuit have ...
Sujit Dey, Vijay Gangaram, Miodrag Potkonjak
EURODAC
1994
IEEE
145views VHDL» more  EURODAC 1994»
14 years 3 months ago
Testability analysis and improvement from VHDL behavioral specifications
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
ICCAD
1995
IEEE
136views Hardware» more  ICCAD 1995»
14 years 2 months ago
A controller-based design-for-testability technique for controller-data path circuits
This paper investigates the effect of the controller on the testability of sequential circuits composed of controllers and data paths. It is shown that even when both the controll...
Sujit Dey, Vijay Gangaram, Miodrag Potkonjak
ASPDAC
1995
ACM
130views Hardware» more  ASPDAC 1995»
14 years 2 months ago
Design for testability using register-transfer level partial scan selection
Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on tes...
Akira Motohara, Sadami Takeoka, Toshinori Hosokawa...