129 search results - page 7 / 26 » A datapath synthesis system for the reconfigurable datapath ... |
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
ISSS
2002
IEEE
14 years 12 days ago
2002
IEEE
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
- Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach ...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...