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» A design platform for 90-nm leakage reduction techniques
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DAC
2004
ACM
13 years 11 months ago
Leakage in nano-scale technologies: mechanisms, impact and design considerations
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...
Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, K...
DAC
2002
ACM
14 years 8 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...
ISQED
2007
IEEE
165views Hardware» more  ISQED 2007»
14 years 1 months ago
On-Line Adjustable Buffering for Runtime Power Reduction
We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, the mainstream techn...
Andrew B. Kahng, Sherief Reda, Puneet Sharma
ISLPED
2005
ACM
101views Hardware» more  ISLPED 2005»
14 years 1 months ago
Defocus-aware leakage estimation and control
Leakage power is one of the most critical issues for ultra-deep submicron technology. Subthreshold leakage depends exponentially on linewidth, and consequently variation in linewi...
Andrew B. Kahng, Swamy Muddu, Puneet Sharma
GLVLSI
2009
IEEE
143views VLSI» more  GLVLSI 2009»
13 years 11 months ago
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos