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ICCAD
2004
IEEE
147views Hardware» more  ICCAD 2004»
14 years 4 months ago
Interval-valued reduced order statistical interconnect modeling
9, IO]. However, unlike the case with static timing, it is not so easy We show how recent advances in the handling of correlated interval representations of range uncertainty can b...
James D. Ma, Rob A. Rutenbar
HPCA
2003
IEEE
14 years 7 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
ICCAD
2003
IEEE
142views Hardware» more  ICCAD 2003»
14 years 4 months ago
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation
The recent demand for system-on-chip RF mixed-signal design and aggressive supply-voltage reduction require chip-level accurate analysis of both the substrate and power delivery s...
Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Ch...
ICCAD
2006
IEEE
112views Hardware» more  ICCAD 2006»
14 years 4 months ago
A new RLC buffer insertion algorithm
Most existing buffering algorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. Even for the approaches...
Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weip...
DAC
2003
ACM
14 years 20 days ago
Realizable RLCK circuit crunching
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Isma...