Sciweavers

1013 search results - page 122 / 203
» A hardware implementation of realloc function
Sort
View
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
14 years 2 days ago
Software Performance Estimation in MPSoC Design
- Estimation tools are a key component of system-level methodologies, enabling a fast design space exploration. Estimation of software performance is essential in current software-...
Márcio Oyamada, Flávio Rech Wagner, ...
ISCA
2003
IEEE
150views Hardware» more  ISCA 2003»
14 years 1 months ago
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
Dan Ernst, Andrew Hamel, Todd M. Austin
ICCD
2001
IEEE
103views Hardware» more  ICCD 2001»
14 years 5 months ago
Fixed-outline Floorplanning through Better Local Search
Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice o...
Saurabh N. Adya, Igor L. Markov
ICCAD
2006
IEEE
100views Hardware» more  ICCAD 2006»
14 years 5 months ago
Nanowire addressing with randomized-contact decoders
— Methods for assembling crossbars from nanowires (NWs) have been designed and implemented. Methods for controlling individual NWs within a crossbar have also been proposed, but ...
Eric Rachlin, John E. Savage
ICCAD
2005
IEEE
100views Hardware» more  ICCAD 2005»
14 years 5 months ago
Performance-centering optimization for system-level analog design exploration
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog ...
Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih C...