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ETS
2006
IEEE
113views Hardware» more  ETS 2006»
14 years 2 months ago
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. strate that these interconnects abstract the interconne...
Alexandre M. Amory, Kees Goossens, Erik Jan Marini...
FCCM
2005
IEEE
142views VLSI» more  FCCM 2005»
14 years 1 months ago
FPGA-Based Vector Processing for Solving Sparse Sets of Equations
The solution to a set of sparse linear equations Ax = b, where A is an n×n sparse matrix and b is an n-element vector, can be obtained using the W-matrix method. An enhanced vect...
Muhammad Z. Hasan, Sotirios G. Ziavras
ICCAD
1996
IEEE
106views Hardware» more  ICCAD 1996»
14 years 3 days ago
Heterogeneous built-in resiliency of application specific programmable processors
Abstract - Using the exibility provided by multiple functionalities we have developed a new approach for permanent fault-tolerance: Heterogeneous BuiltIn-Resiliency (HBIR). HBIR p...
Kyosun Kim, Ramesh Karri, Miodrag Potkonjak
MICRO
1999
IEEE
108views Hardware» more  MICRO 1999»
14 years 6 days ago
Exploiting ILP in Page-based Intelligent Memory
This study compares the speed, area, and power of di erent implementations of Active Pages OCS98], an intelligent memory system which helps bridge the growing gap between processo...
Mark Oskin, Justin Hensley, Diana Keen, Frederic T...
DAC
2006
ACM
14 years 9 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards