46 search results - page 5 / 10 » A high performance bus communication architecture through bu... |
TECS
2008
13 years 7 months ago
2008
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication archite...
SPIESR
1996
13 years 9 months ago
1996
Multimedia interfaces increase the need for large image databases, capable of storing and reading streams of data with strict synchronicity and isochronicity requirements. In orde...
NOCS
2009
IEEE
14 years 2 months ago
2009
IEEE
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
ISSS
2002
IEEE
14 years 25 days ago
2002
IEEE
This paper presents a new technique for global energy optimization through coordinated functional partitioning and speed selection for embedded processors interconnected by a high...