13 search results - page 1 / 3 » A low-power SRAM using bit-line charge-recycling technique |
ISCAS
2003
IEEE
14 years 21 days ago
2003
IEEE
This paper proposes a shared-capacitor charge-sharing ROM (SCCS-ROM). The SCCS-ROM reduces the swing voltage using the charge-sharing technique of the charge-sharing ROM (CSROM) [...
ISLPED
2007
ACM
13 years 9 months ago
2007
ACM
We propose a new low-power SRAM using bit-line Charge Recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obtain...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
In this paper, we provide an analytical framework to study the inter-cell and intra-cell bit-line coupling when it is superimposed with the ground bounce effect and show how those...
ISQED
2008
IEEE
14 years 1 months ago
2008
IEEE
We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SR...
ISQED
2010
IEEE
13 years 9 months ago
2010
IEEE
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering ...