76 search results - page 1 / 16 » A methodology to improve timing yield in the presence of pro... |
DAC
2004
ACM
13 years 11 months ago
2004
ACM
The ability to control the variations in IC fabrication process is rapidly diminishing as feature sizes continue towards the sub-100 nm regime. As a result, there is an increasing...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
- Exceptionally leaky transistors are increasingly more frequent in nano-scale technologies due to lower threshold voltage and its increased variation. Such leaky transistors may e...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
DATE
2005
IEEE
13 years 9 months ago
2005
IEEE
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
With the emerging process variations in fabrication, the traditional corner-based timing optimization techniques become prohibitive. Buffer insertion is a very useful technique fo...