76 search results - page 5 / 16 » A methodology to improve timing yield in the presence of pro... |
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
- Advanced process technologies impose more significant challenges especially when manufactured circuits exhibit substantial process variations. Consideration of process variations...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
A new algorithm is presented that combines performance and variation objectives in a behavioural model for a given analogue circuit topology and process. The tradeoffs between per...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
Based on a timing yield model, a statistical static timing analysis technique is proposed. This technique preserves existing methodology by selecting a “device file setting” ...
ASPDAC
2009
ACM
14 years 2 months ago
2009
ACM
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. In the presence of process variations, wo...