75 search results - page 6 / 15 » A multiple clocking scheme for low power RTL design |
ICC
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— In this paper, we investigate the problem of minimizing the average transmission power of users while guaranteeing the average delay constraints in time-varying uplink ...
DAC
2005
ACM
13 years 10 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
GLVLSI
2002
IEEE
14 years 1 months ago
2002
IEEE
We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ...
ASPDAC
2007
ACM
14 years 18 days ago
2007
ACM
Multiple supply voltage (MSV) is one of the most effective schemes to achieve low power, but most works are based on logic level. A few recent works are based on physical level but...
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...