179 search results - page 6 / 36 » A new test pattern generation method for delay fault testing |
DDECS
2007
IEEE
14 years 1 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
DATE
2000
IEEE
13 years 12 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
ETS
2006
IEEE
14 years 1 months ago
2006
IEEE
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
DATE
2002
IEEE
14 years 15 days ago
2002
IEEE
Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of eac...