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ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
14 years 1 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
HPCA
2005
IEEE
14 years 1 months ago
Heat Stroke: Power-Density-Based Denial of Service in SMT
In the past, there have been several denial-of-service (DOS) attacks which exhaust some shared resource (e.g., physical memory, process table, file descriptors, TCP connections) ...
Jahangir Hasan, Ankit Jalote, T. N. Vijaykumar, Ca...
ICDCS
2010
IEEE
13 years 11 months ago
A Spinning Join That Does Not Get Dizzy
— As network infrastructures with 10 Gb/s bandwidth and beyond have become pervasive and as cost advantages of large commodity-machine clusters continue to increase, research and...
Philip Werner Frey, Romulo Goncalves, Martin L. Ke...
FPL
2007
Springer
97views Hardware» more  FPL 2007»
13 years 11 months ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
ISCAS
1995
IEEE
91views Hardware» more  ISCAS 1995»
13 years 11 months ago
An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays
Abstract -- Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmab...
W. Eatherton, J. Kelly, T. Schiefelbein, H. Pottin...