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» A snap-on placement tool
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VLSID
2002
IEEE
119views VLSI» more  VLSID 2002»
14 years 8 months ago
Reducing Library Development Cycle Time through an Optimum Layout Create Flow
One of the major roadblocks in reduction of library generation cycle time is the layout generation phase. The two methods of doing automatic layout generation are synthesis and mig...
Rituparna Mandal, Dibyendu Goswami, Arup Dash
MICCAI
2000
Springer
13 years 11 months ago
Pre- and Intra-operative Planning and Simulation of Percutaneous Tumor Ablation
We developed a software tool for pre-operative simulation and planning, and intra-operative guidance, of minimally invasive tumor ablation, including radiofrequency-, laser- and cr...
Torsten Butz, Simon K. Warfield, Kemal Tuncali, St...
DAC
2008
ACM
14 years 8 months ago
Topological routing to maximize routability for package substrate
Compared with on-chip routers, the existing commercial tools for off-chip routing have a much lower routability and often result in a large number of unrouted nets for manual rout...
Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He...
DAC
2003
ACM
14 years 8 months ago
Dynamic hardware/software partitioning: a first approach
Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy co...
Greg Stitt, Roman L. Lysecky, Frank Vahid
DATE
2007
IEEE
80views Hardware» more  DATE 2007»
14 years 2 months ago
Double-via-driven standard cell library design
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited ca...
Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Run...