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HPCA
2006
IEEE
14 years 8 months ago
A decoupled KILO-instruction processor
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
Miquel Pericàs, Adrián Cristal, Rube...
ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
13 years 5 months ago
Memory organization and data layout for instruction set extensions with architecturally visible storage
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leb...
FSE
1993
Springer
148views Cryptology» more  FSE 1993»
13 years 11 months ago
Design Principles for Dedicated Hash Functions
Abstract. Dedicated hash functions are cryptographically secure compression functions which are designed specifically for hashing. They intend to form a practical alternative for ...
Bart Preneel
ITC
1998
IEEE
95views Hardware» more  ITC 1998»
13 years 12 months ago
Native mode functional test generation for processors with applications to self test and design validation
New methodologies based on functional testing and built-in self-test can narrow the gap between necessary solutions and existing techniques for processor validation and testing. W...
Jian Shen, Jacob A. Abraham
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
13 years 12 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail