29 search results - page 5 / 6 » Accurate Area and Delay Estimators for FPGAs |
DAC
2004
ACM
14 years 8 months ago
2004
ACM
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...
ICCAD
1991
IEEE
13 years 11 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
ISQED
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
FPL
2007
Springer
14 years 1 months ago
2007
Springer
An important step in Heterogeneous System Development is Hardware/Software Partitioning. This process involves exploring a huge design space. By using profiling to select hot-spo...