32 search results - page 3 / 7 » Accurate Fault Modeling and Fault Simulation of Resistive Br... |
HPCA
2009
IEEE
14 years 10 months ago
2009
IEEE
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
ICCAD
1994
IEEE
14 years 1 months ago
1994
IEEE
We consider the problem of testing for delay faults in macrobased circuits. Macro-based circuits are obtained as a result of technology mapping. Gate-level fault models cannot be ...
VTS
2000
IEEE
14 years 2 months ago
2000
IEEE
Abstract: This paper presents a notation for describing functional fault models, which may occur in memory devices. Using this notation, the space of all possible memory faults has...
ITC
1991
IEEE
14 years 1 months ago
1991
IEEE
Two approaches have been used to balance the cost of generating e ective tests for ICs and the need to increase the ICs' quality level. The rst approach favorsusing high-leve...
ITC
2002
IEEE
14 years 2 months ago
2002
IEEE
The advantage to “one test at a time” fault diagnosis is its ability to implicate the components of complicated defect behaviors. The disadvantage is the large size and opacit...