Sciweavers

193 search results - page 7 / 39
» Accurate power estimation for large sequential circuits
Sort
View
ICCAD
2004
IEEE
128views Hardware» more  ICCAD 2004»
14 years 4 months ago
Power estimation for cycle-accurate functional descriptions of hardware
— Cycle-accurate functional descriptions (CAFDs) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent in...
Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj...
MTV
2007
IEEE
118views Hardware» more  MTV 2007»
14 years 2 months ago
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...
Wang-Dauh Tseng, Lung-Jen Lee
DATE
2005
IEEE
158views Hardware» more  DATE 2005»
14 years 1 months ago
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT) leakage, results in the large incr...
Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
ISQED
2009
IEEE
133views Hardware» more  ISQED 2009»
14 years 2 months ago
A novel ACO-based pattern generation for peak power estimation in VLSI circuits
Estimation of maximal power consumption is an essential task in VLSI circuit realizations since power value significantly affects the reliability of the circuits. The key issue o...
Yi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, Ya-Hsi...
DATE
2009
IEEE
202views Hardware» more  DATE 2009»
14 years 2 months ago
Design as you see FIT: System-level soft error analysis of sequential circuits
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
Daniel Holcomb, Wenchao Li, Sanjit A. Seshia