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» Active leakage power optimization for FPGAs
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ISQED
2009
IEEE
91views Hardware» more  ISQED 2009»
14 years 5 months ago
Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments
We propose a novel design flow for mismatch and processvariation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an 8 × 8 APS array is de...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
14 years 4 months ago
Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities
Traditionally, active power has been the primary source of power dissipation in CMOS designs. Although, leakage power is becoming increasingly more important as technology feature...
Po-Kuan Huang, Soheil Ghiasi
DATE
2010
IEEE
145views Hardware» more  DATE 2010»
14 years 3 months ago
Energy-efficient real-time task scheduling with temperature-dependent leakage
Abstract--Leakage power consumption contributes significantly to the overall power dissipation for systems that are manufactured in advanced deep sub-micron technology. Different f...
Chuan-Yue Yang, Jian-Jia Chen, Lothar Thiele, Tei-...
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
14 years 5 months ago
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints
Sleep transistor insertion is one of today’s most promising and widely adopted solutions for controlling stand-by leakage power in nanometer circuits. Although single-cycle powe...
Andrea Calimera, Luca Benini, Enrico Macii
CASES
2006
ACM
14 years 4 months ago
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations
Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for lowthroughput, energy-constrained applications. Un...
Mark Hempstead, Gu-Yeon Wei, David Brooks