144 search results - page 18 / 29 » Adapting cache line size to application behavior |
DAC
2004
ACM
14 years 8 months ago
2004
ACM
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
ATAL
2003
Springer
13 years 11 months ago
2003
Springer
We describe a general mechanism for adaptation in multiagent systems in which agents modify their behavior based on their memory of past events. These behavior changes can be elic...
ISCA
2002
IEEE
14 years 9 days ago
2002
IEEE
The importance of the Translation Lookaside Buffer (TLB) on system performance is well known. There have been numerous prior efforts addressing TLB design issues for cutting down ...
ACMMSP
2005
ACM
14 years 29 days ago
2005
ACM
In this work we investigate the impact of evolving memory system features, such as large on-chip caches, automatic prefetch, and the growing distance to main memory on 3D stencil ...
ISCA
2000
IEEE
13 years 11 months ago
2000
IEEE
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...