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VLSID
2004
IEEE
112views VLSI» more  VLSID 2004»
16 years 4 months ago
Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests
IDDQ test is a valuable test method for semiconductor manufacturers. However, its effectiveness is reduced for deep sub-micron technology chips due to rising background leakage. C...
Sagar S. Sabade, D. M. H. Walker
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
16 years 4 months ago
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is...
Irith Pomeranz, Sudhakar M. Reddy
ICCAD
2001
IEEE
113views Hardware» more  ICCAD 2001»
16 years 1 months ago
The Design and Optimization of SOC Test Solutions
1 We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique ar...
Erik Larsson, Zebo Peng, Gunnar Carlsson
ISSRE
2008
IEEE
15 years 11 months ago
Static Detection of Redundant Test Cases: An Initial Study
As software systems evolve, the size of their test suites grow due to added functionality and customer-detected defects. Many of these tests may contain redundant elements with pr...
Nuo Li, Patrick Francis, Brian Robinson
QSIC
2007
IEEE
15 years 10 months ago
Testing against Natural Language Requirements
: Testing against natural language requirements is the standard approach for system and acceptance testing. This test is often performed by an independent test organization unfamil...
Harry M. Sneed