161 search results - page 3 / 33 » An Analysis of Delay Based PUF Implementations on FPGA |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
We present a de-layered protocol engine for termination of 40Gbps TCP connections using a reconfigurable FPGA silicon platform. This protocol engine is designed for a planned att...
FPGA
1999
ACM
13 years 12 months ago
1999
ACM
In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
ERSA
2008
13 years 9 months ago
2008
This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks...
CHES
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. Many Field-Programmable Gate Array (FPGA) based systems utilize third-party intellectual property (IP) in their development. When they are deployed in non-networked envir...