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» An Effective Diagnosis Method to Support Yield Improvement
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ITC
2003
IEEE
149views Hardware» more  ITC 2003»
14 years 23 days ago
On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures
Diagnosing failing vectors in a Built-In Self Test (BIST) environment is a difficult task because of the highly compressed signature coming out of the Multiple Input Shift Regist...
Ramesh C. Tekumalla
ICCAD
2009
IEEE
92views Hardware» more  ICCAD 2009»
13 years 5 months ago
How to consider shorts and guarantee yield rate improvement for redundant wire insertion
This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield ra...
Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak
DATE
2007
IEEE
86views Hardware» more  DATE 2007»
14 years 1 months ago
Reduction of detected acceptable faults for yield improvement via error-tolerance
Error-tolerance is an innovative way to enhance the effective yield of IC products. Previously a test methodology based on error-rate estimation to support error-tolerance was pro...
Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer
ATS
2009
IEEE
135views Hardware» more  ATS 2009»
14 years 2 months ago
On Scan Chain Diagnosis for Intermittent Faults
Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Sca...
Dan Adolfsson, Joanna Siew, Erik Jan Marinissen, E...
DATE
2006
IEEE
95views Hardware» more  DATE 2006»
14 years 1 months ago
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs
The ever increasing usage of microprocessor devices is sustained by a high volume production that in turn requires a high production yield, backed by a controlled process. Fault d...
Paolo Bernardi, Ernesto Sánchez, Massimilia...