76 search results - page 5 / 16 » An Estimation Methodology for Designing Instruction Cache Me... |
GLVLSI
2010
IEEE
13 years 9 months ago
2010
IEEE
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...
ISLPED
2005
ACM
14 years 29 days ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
GECCO
2004
Springer
14 years 24 days ago
2004
Springer
Portable embedded systems are being driven by consumer demands to be thermally efficient, perform faster, and have longer battery life. To design such a system, various hardware un...
CASES
2010
ACM
13 years 5 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
RTAS
1996
IEEE
13 years 11 months ago
1996
IEEE
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...