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ISSS
1995
IEEE
115views Hardware» more  ISSS 1995»
13 years 11 months ago
A system level design methodology for the optimization of heterogeneous multiprocessors
This paper presents a system level design methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. These heterogeneous systems,...
Markus Schwiegershausen, Peter Pirsch
VLSID
2010
IEEE
211views VLSI» more  VLSID 2010»
13 years 11 months ago
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM
A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nanoCMOS static random access memory (SRAM) is presented. A 45nm single-end...
Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dh...
DAC
2006
ACM
14 years 8 months ago
A new LP based incremental timing driven placement for high performance designs
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...
Tao Luo, David Newmark, David Z. Pan
MP
1998
109views more  MP 1998»
13 years 7 months ago
Rounding algorithms for covering problems
In the last 25 years approximation algorithms for discrete optimization problems have been in the center of research in the fields of mathematical programming and computer science...
Dimitris Bertsimas, Rakesh V. Vohra
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 4 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He