203 search results - page 8 / 41 » An O(nlogn) time algorithm for optimal buffer insertion |
ICCAD
2003
IEEE
14 years 20 days ago
2003
IEEE
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
ISLPED
2006
ACM
14 years 1 months ago
2006
ACM
—The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or alteri...
ISLPED
2007
ACM
13 years 9 months ago
2007
ACM
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Antenna effect may damage gate oxides during plasma-based fabrication process. The antenna ratio of total exposed antenna area to total gate oxide area is directly related to the ...