20 search results - page 3 / 4 » An improved algorithm for tor circuit scheduling |
DATE
2002
IEEE
14 years 14 days ago
2002
IEEE
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
DAC
1998
ACM
13 years 11 months ago
1998
ACM
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
DAC
2008
ACM
13 years 9 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Dynamic voltage scaling (DVS) circuits have been widely adopted in many computing systems to provide tradeoff between performance and power consumption. The effective use of energ...