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» An on Chip ADC Test Structure
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ISCAS
2006
IEEE
121views Hardware» more  ISCAS 2006»
14 years 1 months ago
Microelectromechanical systems in 3D SOI-CMOS: sensing electronics embedded in mechanical structures
— We discuss the design of CMOS MEMS in a 3D SOI-CMOS technology. We present layout architectures, preliminary mechanics modeling using finite element analysis and release proce...
Francisco Tejada, Andreas G. Andreou
DCC
2007
IEEE
14 years 7 months ago
Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces
Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software de...
Milena Milenkovic, Aleksandar Milenkovic, Martin B...
DDECS
2007
IEEE
101views Hardware» more  DDECS 2007»
13 years 7 months ago
A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling
—A Low noise and low power CMOS Image Sensor (CIS) with pixel-level Correlated Double Sampling (CDS) is proposed. As the pixel readout circuit using source follower is major read...
Dongsoo Kim, Gunhee Han
ITC
2003
IEEE
168views Hardware» more  ITC 2003»
14 years 22 days ago
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy
Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and do...
Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen ...
ET
2010
98views more  ET 2010»
13 years 6 months ago
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
Stephan Eggersglüß, Görschwin Fey,...