117 search results - page 6 / 24 » An optimal algorithm for sizing sequential circuits for indu... |
TVLSI
2010
13 years 2 months ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
DAC
2008
ACM
13 years 9 months ago
2008
ACM
This paper presents an automated analog synthesis tool for topology generation and subsequent circuit sizing. Though sizing is indispensable, the paper mainly concentrates on topo...
DAC
2009
ACM
14 years 4 days ago
2009
ACM
The progress of GPU (Graphics Processing Unit) technology opens a new avenue for boosting computing power. This work is an attempt to exploit GPU for accelerating VLSI circuit opt...
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
- This paper presents an optimal algorithm for solving the problem of simultaneous fanout optimization and routing tree construction for an ordered set of critical sinks. The algor...
ASPDAC
2004
ACM
14 years 27 days ago
2004
ACM
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...