7 search results - page 1 / 2 » An overview of on-chip interconnect variation |
124
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ISQED
2007
IEEE
15 years 10 months ago
2007
IEEE
Abstract—A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected...
131
Voted
DAC
2001
ACM
16 years 4 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
131
Voted
ISCAS
2007
IEEE
15 years 9 months ago
2007
IEEE
Abstract— This paper reports the design of a high performance, adaptive low/high swing CMOS driver circuit (mj–driver) suitable for driving of global interconnects with large c...
115
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DAC
1998
ACM
16 years 4 months ago
1998
ACM
Because magnetic e ects have a much longer spatial range than electrostatic e ects, an interconnect line with large inductance will be sensitive to distant variations in interconn...
126
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SLIP
2009
ACM
15 years 10 months ago
2009
ACM
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of curre...