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    ICCAD
    2004
    IEEE
    145views Hardware» more  ICCAD 2004»
    Accurate estimation of global buffer delay within a floorplan
    14 years 5 months ago
    Accurate estimation of global buffer delay within a floorplan
    Download  www.ece.umn.edu
    Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
    Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar,...
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    DAC
    2004
    ACM
    128views Computer Architecture» more  DAC 2004»
    Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
    14 years 9 months ago
    Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
    Download  vlsi.ece.wisc.edu
    With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...
    Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
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    DAC
    2009
    ACM
    135views Computer Architecture» more  DAC 2009»
    Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis
    14 years 9 months ago
    Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis
    Download  www12.informatik.uni-erlangen.de
    In this paper, a design method for automotive architectures is proposed. The two main technical contributions are (i) a novel hardware/software architecture encoding that unifies ...
    Jürgen Teich, Martin Lukasiewycz, Michael Gla...
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    DAC
    1998
    ACM
    127views Computer Architecture» more  DAC 1998»
    Design Reliability - Estimation through Statistical Analysis of Bug Discovery Data
    14 years 9 months ago
    Design Reliability - Estimation through Statistical Analysis of Bug Discovery Data
    Download  www.research.ibm.com
    Statistical analysis of bug discovery data is used in the software industry to check the quality of the testing process and estimate the reliability of the tested program. In this...
    Yossi Malka, Avi Ziv
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    DAC
    2007
    ACM
    152views Computer Architecture» more  DAC 2007»
    Global Critical Path: A Tool for System-Level Timing Analysis
    14 years 9 months ago
    Global Critical Path: A Tool for System-Level Timing Analysis
    Download  research.microsoft.com
    An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
    Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...
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