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DAC
2008
ACM
14 years 9 months ago
Enhancing timing-driven FPGA placement for pipelined netlists
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
Kenneth Eguro, Scott Hauck
DAC
2001
ACM
14 years 9 months ago
Circuit-based Boolean Reasoning
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit...
Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi
DAC
2001
ACM
14 years 9 months ago
Future Performance Challenges in Nanometer Design
We highlight several fundamental challenges to designing highperformance integrated circuits in nanometer-scale technologies (i.e. drawn feature sizes < 100 nm). Dynamic power ...
Dennis Sylvester, Himanshu Kaul
DAC
2002
ACM
14 years 9 months ago
Transformation based communication and clock domain refinement for system design
The ForSyDe methodology has been developed for system level design. In this paper we present formal transformation methods for the refinement of an abstract and formal system mode...
Ingo Sander, Axel Jantsch
DAC
2003
ACM
14 years 9 months ago
Quantum-dot cellular automata: computing by field polarization
As CMOS technology continues its monotonic shrink, computing with quantum dots remains a goal in nanotechnology research. Quantum-dot cellular automata (QCA) is a paradigm for low...
Gary H. Bernstein