As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
This paper presents a new algorithm based on Integrated Congruence transform for the analysis of both uniform and nonuniform transmission lines. The key advantage of the proposed ...
Detailed electromagnetic analysis of three-dimensional structures in multilayered dielectric media is critical for automatic generation of equivalent circuit models for the interc...
Ben Song, Zhenhai Zhu, John D. Rockway, Jacob Whit...
This paper presents the design and the laboratory results of an integrated half-bridge driver for power electronic systems in a 0.35 µm Bipolar CMOS DMOS (BCD) technology. The pr...
Francesco D'Ascoli, Luca Bacciarelli, Massimiliano...