60 search results - page 10 / 12 » Architectural Frameworks for MPP Systems on a Chip |
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
CODES
2007
IEEE
13 years 11 months ago
2007
IEEE
System-level and Platform-based design, along with Transaction Level modeling (TLM) techniques and languages like SystemC, appeared as a response to the ever increasing complexity...
DATE
2010
IEEE
14 years 28 days ago
2010
IEEE
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
DATE
2010
IEEE
14 years 28 days ago
2010
IEEE
There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumpti...
DFT
2006
IEEE
13 years 9 months ago
2006
IEEE
As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. ...