1381 search results - page 80 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
DAC
1998
ACM
14 years 9 months ago
1998
ACM
This paper presents a method for power and ground (p/g) network routing for high speed CMOS chips with multiple p/g pads. Our objective is not to reduce the total amount of the gr...
CASES
2007
ACM
14 years 5 days ago
2007
ACM
The development of robust and efficient synthesis tools is important if asynchronous design is to gain more widespread acceptance. Syntax-directed translation is a powerful synthe...
ISCA
2010
IEEE
14 years 1 months ago
2010
IEEE
Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless s...
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
DAC
2009
ACM
14 years 9 months ago
2009
ACM
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...