1381 search results - page 8 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custo...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
An important aspect of Design for Yield for embedded SRAM is identifying the expected worst case behavior in order to guarantee that sufficient design margin is present. Previousl...
DAC
2009
ACM
14 years 9 months ago
2009
ACM
With aggressive technology scaling, SRAM design has been seriously challenged by the difficulties in analyzing rare failure events. In this paper we propose to create statistical ...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...