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    DAC
    2006
    ACM
    148views Computer Architecture» more  DAC 2006»
    Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
    14 years 10 months ago
    Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
    Download  www.ee.ucla.edu
    Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
    Yu Hu, Yan Lin, Lei He, Tim Tuan
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    DAC
    1999
    ACM
    114views Computer Architecture» more  DAC 1999»
    Hypergraph Partitioning with Fixed Vertices
    14 years 10 months ago
    Hypergraph Partitioning with Fixed Vertices
    Download  vlsicad.ucsd.edu
    We empirically assess the implications of fixed terminals for hypergraph partitioning heuristics. Our experimental testbed incorporates a leading-edge multilevel hypergraph partit...
    Andrew E. Caldwell, Andrew B. Kahng, Igor L. Marko...
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    CASES
    2009
    ACM
    130views System Software» more  CASES 2009»
    An accelerator-based wireless sensor network processor in 130nm CMOS
    14 years 4 months ago
    An accelerator-based wireless sensor network processor in 130nm CMOS
    Download  www.eecs.harvard.edu
    Networks of ultra-low-power nodes capable of sensing, computation, and wireless communication have applications in medicine, science, industrial automation, and security. Over the...
    Mark Hempstead, Gu-Yeon Wei, David Brooks
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    DAC
    2006
    ACM
    141views Computer Architecture» more  DAC 2006»
    Timing-based delay test for screening small delay defects
    14 years 10 months ago
    Timing-based delay test for screening small delay defects
    Download  www.engr.uconn.edu
    The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
    Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
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    ISCAS
    2006
    IEEE
    122views Hardware» more  ISCAS 2006»
    256-channel integrated neural interface and spatio-temporal signal processor
    14 years 3 months ago
    256-channel integrated neural interface and spatio-temporal signal processor
    Download  www.eecg.toronto.edu
    Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
    J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...
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